A low-power high-SFDR CMOS direct digital frequency synthesizer

—A low-power high-SFDR CMOS direct digital frequency synthesizer (DDFS) is presented. Several design techniques, including a cell-based lookup table, a power aware parameters selection method, a reduced multiplier, a speededup adder/subtracter, an extra pipeline stage, and supply voltage scaling, are used to make the design more easily synthesizable and much more power efficient. A synthesized 0.35-µm DDFS, with an SFDR of -100 dBc, runs up to 100

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
• Keywords: Cell-based Lookup Table, Digital Frequency Synthesizer, ISCAS 2005, Power Aware Parameters