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ASPDAC
2005
ACM

Low-power techniques for network security processors

14 years 1 months ago
Low-power techniques for network security processors
Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiu
Added 13 Oct 2010
Updated 13 Oct 2010
Type Conference
Year 2005
Where ASPDAC
Authors Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu
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