A Low-Speed BIST Framework for High-Performance Circuit Testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a Design-for-Test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed.

• Type: Conference
• Year: 2000
• Where: VTS
• Authors: Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
• Keywords: Hardware, Low Performance Testers, Performance Integrated Circuits, Various Implementation Aspects, VTS 2000