On LUT Cascade Realizations of FIR Filters

This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the distributed arithmetic of a finite impulse response (FIR) filter. Then, it shows a method to realize the WS function by an LUT cascade with k-input q-output cells. Furthermore, it 1) shows that LUT cascade realizations require much smaller memory than the single ROM realizations; 2) presents new design method for a WS function by arithmetic decomposition, and 3) shows design results of FIR filters using FPGAs with embedded memories.

• Type: Conference
• Year: 2005
• Where: DSD
• Authors: Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki
• Keywords: DSD 2005, Hardware, LUT Cascade, Q-output Ws Function, WS Function