MAJC-5200: A High Performance Microprocessor for Multimedia Computing

The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruction level parallelism via a very long instruction word architecture VLIW and SIMD. The rst implementation, MAJC-5200, includes some key features of MAJC to realize a high performance multimedia processor. Two CPUs running at 500 MHz are integrated into the chip to provide 6.16 GFLOPS and 12.33 GOPS with high speed interfaces providing a peak input-output I O data rate of more than 4.8 G Bytes second. The chip is suitable for a number of applications including graphics multimedia processing for high-end set-top boxes, digital voice processing for telecommunications, and advanced imaging.

• Type: Conference
• Year: 2000
• Where: IPPS
• Authors: Subramania Sudharsanan
• Keywords: Distributed And Parallel Computing, Instruction Level Parallelism, Instruction Word Architecture, IPPS 2000, Peak Input-output I