Memory Bandwidth Limitations of Future Microprocessors

This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory latencies do so at the expense of increased bandwidth requirements. Using a decomposition of execution time, we show that for modern processors that employ aggressive memory latency tolerance techniques, wasted cycles due to insufficient bandwidth generally exceed those due to raw memory latencies. Given the importance of maximizing memory bandwidth, we calculate effective pin bandwidth, then estimate optimal effective pin bandwidth. We measure these quantities by determining the amount by which both caches and minimal-traffic caches filter accesses to the lower levels of the memory hierarchy. We see that there is a gap that can exceed two orders of magnitude between the total memory traffic generated by caches and the minimal-traffic caches--implying that the potential exists to increase effective pin bandwidth s...

• Type: Conference
• Year: 1996
• Where: ISCA
• Authors: Doug Burger, James R. Goodman, Alain Kägi
• Keywords: Effective Pin Bandwidth, Hardware, ISCA 1996, Memory Latencies, Pin Bandwidth