Memory mapped ECC: low-cost error protection for last level caches

This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processor resources become constrained and error propensity increases. The continuing decrease in SRAM cell size and the growing capacity of caches increases the likelihood of errors in SRAM arrays. To address this, redundant information can be used to correct a value after an error occurs. Information redundancy is typically provided through errorcorrecting codes (ECC), which append bits to every SRAM row and increase the array’s area and energy consumption. We make three observations regarding error protection and utilize them in our architecture: (1) much of the data in a cache is replicated throughout the hierarchy and is inherently redundant; (2) error-detection is necessary for every cache access and is cheaper than error correction, which is very infrequent; (3) redundant information for correction need not ...

• Type: Conference
• Year: 2009
• Where: ISCA
• Authors: Doe Hyun Yoon, Mattan Erez
• Keywords: Error Correction, Error Propensity Increases, Hardware, ISCA 2009, Memory Mapped ECC