Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors

Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case execution (WCET) bounds of tasks. Designers of these systems are forced to avoid state-of-the-art processors due to their inherent architectural complexity (such as out-oforder instruction scheduling) that results in non-determinism. This work addresses this problem by providing novel pipeline analysis techniques for characterizing the worst-case behavior of real-time systems on modern processor architectures. We introduce methods to capture (“snapshot”) pipeline state and to subsequently perform a “merge” of previously captured snapshots. We prove that our pipeline analysis correctly preserves worst-case timing behavior on out-of-order (OOO) processor pipelines. We further specifically show that anomalous pipeline effects, effectively dilating timing, are preserved by our method. To the best of our kno...

• Type: Conference
• Year: 2008
• Where: RTSS
• Authors: Sibin Mohan, Frank Mueller
• Keywords: Applied Computing, Pipeline Analysis, Pipeline Analysis Techniques, RTSS 2008, Worst-case