The goal of the research is twofold First, the derivation of a design methodology for FIR filters implementation based on Residue Number System (RNS), aiming at power, delay and hardware complexity reduction comparing with conventional binary implementations. Second, a CAD tool development, which generates synthesizable VHDL description of any RNS system design, in automatic way. This tool can derive RNS Full Adderbased DSP architectures consisting of FIR, Scaling, Converters, Multiplication and Accumulation units.
Dimitrios Soudris, K. Sgouropoulos, Konstantinos T