MiniBit: bit-width optimization via affine arithmetic

MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing circuit area. Our range analysis technique identifies the number of integer bits required. For precision analysis, we employ a semi-analytical approach with analytical error models in conjunction with adaptive simulated annealing to find the optimum number of fraction bits. Improvements for a given design reduce area and latency by up to 20% and 12% respectively, over optimum uniform fraction bit-widths on a Xilinx Virtex-4 FPGA. Categories and Subject Descriptors B.5.2 [Register-Transfer-Level Implementation]: Design Aids--automatic synthesis, optimization General Terms Algorithms, Design, Experimentation, Performance Keywords Affine Arithmetic, Bit-Width, Fixed-Point, FPGA, Simulated Annealing

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
• Keywords: Adaptive Simulated Annealing, DAC 2005, Design Automation, Fixed-point Signals, Optimum Uniform Fraction