Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video

Abstract— The mixed-signal processor performs digital vectormatrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell combines single-bit dynamic storage, binary multiplication, and zerolatency analog accumulation. Matrix coefficients are stored in a bit-parallel form. Delta-sigma analog-to-digital conversion of the analog array outputs is combined with oversampled unary coding of the digital inputs. Sorting of unary inputs results in at most a single input line transition for arbitrary multi-bit inputs. This amounts to a linear gain in energy efficiency of the computational array in the number of bits of the input vector. The 256 × 128 CID/DRAM processor with integrated 128 deltasigma ADCs measures 3 mm × 3 mm in 0.5 µm CMOS and delivers 6.5 GMACS dissipating 5.9 mW of power. CID/DRAM array dynamic power dissipation is reduced by a factor of four through sorting 8-bit inputs.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Rafal Karakiewicz, Roman Genov
• Keywords: Analog Array Outputs, Analog fine-grain Parallel, Arbitrary Multi-bit Inputs, ISCAS 2005