Minimizing leakage: What if every gate could have its individual threshold voltage?

Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduce a circuit’s power dissipation. Even though technologically not possible today, this paper hypothesizes that the design would allow for choosing a gate’s from a continuous domain in order to explore options for future improvements. That is, the design goal consists in selecting a gate’s delay such that both the circuit’s delay and its power consumption assumes minimal values. Since the resulting optimization problem is multi-dimensional and might also contain local optima, this paper utilizes genetic algorithms for this task. On a selection of the well-known ISCACS test suite, the genetic algorithms reduced the circuits’ leakage values by about 20-50%; with respect to non-optimized circuits, the improvement is about 60-80%. KEY WORDS Genetic Algorithms, Real-World Application, Low-Power VLSI, Optim...

• Type: Conference
• Year: 2007
• Where: AIA
• Authors: Ralf Salomon, Frank Sill, Dirk Timmermann
• Keywords: AIA 2007, Artificial Intelligence, Circuit’s Power Dissipation, Consuming Integrated Circuits, Genetic Algorithms