Modeling QCA for area minimization in logic synthesis

Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device improvements. While significant advancements in nanotechnology devices have been achieved, much work is required to integrate these technologies into the existing design methodologies. Given that the physical design paradigm of each nanotechnology will be significantly different than that of traditional silicon circuits, the underlying cost functions used in optimization algorithms ut the design abstraction hierarchy must be altered. Because nanotechnologies are not as well developed and od as silicon devices, abstraction will initially result in less accurate models. However, if models are developed and augmented as nanotechnologies continue to evolve, the transition from CMOS-based design to nano-based design will be relatively seamless. er details the logic-level abstraction process for area minimization for on...

• Type: Conference
• Year: 2003
• Where: GLVLSI
• Authors: Nadine Gergel, Shana Craft, John Lach
• Keywords: Design, Design Abstraction Hierarchy, GLVLSI 2003, Nanotechnologies, VLSI