Module assignment for pin-limited designs under the stacked-Vdd paradigm

Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficiently assigning modules at the floorplanning level so as to reuse currents between the Vdd domains, and minimize the power wasted during the operation of the circuit. Experimental results on a DLX architecture show that compared with assigning modules to different Vdd rails using a bin-packing technique, the circuit generated by our algorithm has 32% lower wasted power, on average. In addition, experiments on a 3D IC example show that our module assignment approach is equally effective in reducing the power waste in 3D ICs. I. MOTIVATIONS AND DESIGN CONSIDERATIONS Due to the increased complexity and elevated power consumption of high performance VLSI circuits, the I/O pin limitation problem has become an important issue in chip design. According to the trend predicted by ITRS [1], one-half to two-thirds of all ...

• Type: Conference
• Year: 2007
• Where: ICCAD
• Authors: Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
• Keywords: Hardware, I/O Pin Limitation, ICCAD 2007, Lower Wasted Power, Pin Limitation Problem