A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths

Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process characterization and yield enhancement. At the same time, hierarchical test approaches are becoming the prevalent means for addressing the size and complexity of large designs and for accommodating the varying individual test needs of each design module. In this paper, we discuss a module diagnosis and design-for-debug methodology through hierarchical test paths. Based on debug information inherently attainable from hierarchical test paths, we outline a diagnosis algorithm that identifies the minimal set of faulty module candidates, under the single faulty module model. We further provide a disambiguation rule to ensure unfailing identification of the single faulty module. Low-cost, design-for-debug techniques are subsequently proposed for establishing the disambiguation rule and for providing a module diagn...

• Type: Conference
• Year: 1999
• Where: DFT
• Authors: Yiorgos Makris, Alex Orailoglu
• Keywords: DFT 1999, Faulty Module, Hierarchical Test, Single Faulty Module, VLSI