A More Precise Model of Noise Based PCMOS Errors

—In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterization proposed here can enable accurate multi-bit models based on fast mathematical extrapolation instead of expensive and slow HSPICE simulations.

• Type: Conference
• Year: 2010
• Where: DELTA
• Authors: Arun Bhanu, Mark S. K. Lau, Keck Voon Ling, Vincent John Mooney III, Anshul Singh
• Keywords: DELTA 2010, Fast Mathematical Extrapolation, Probabilistic Cmos, Probabilistic Gates