More Wires and Fewer LUTs: A Design Methodology for FPGAs

In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optimal solution. In this paper, we present an FPGA design methodology to eciently nd well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is eective in developing well-balanced FPGAs.

• Type: Conference
• Year: 1998
• Where: FPGA
• Authors: Atsushi Takahara, Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Kazuhiro Hayashi, Akihiro Tsutsui, Takaki Ichimori, Ken-nosuke Fukami
• Keywords: FPGA, FPGA 1998, Logic Blocks, Well-balanced Fpgas