Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy

In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. This method rst synthesizes a design speci cation in a ne-grained way so that functional clusters can be preserved based on the structural nature of the design speci cation. Then, it applies a hierarchical set-covering partitioning method to form the nal FPGA partitions. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarchy. Experimental results on a number of benchmarks and industrial designs demonstrate that I O limits are the bottleneck for CLB utilization when applying a traditional multiple-FPGA synthesis method on attened netlists. In contrast, by fully exploiting the design structural hierarchy during the multiple-FPGA partitioning, our proposed method produces fewer FPGA partitions with higher CLB and lower I O-pin utilizations.

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Wen-Jong Fang, Allen C.-H. Wu
• Keywords: Computer Architecture, DAC 1997, Design Speci Cation, Partitioning Method, Set-covering Partitioning Method