Multiplier energy reduction through bypassing of partial products

Designof portablebattery operatedmultimediadevices requires energy-ecient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital multiplier based on dynamic bypassing of partial products. The bypassing elements incorporated into the multiplier hardware eliminate redundant signal transitions, which appear within the carry-saveadderswhenthe partialproductiszero. Simulations on the real-life DCT data show that the proposed approach can improve power saving of related methods by 12%, while jointly with them, it reduces the power consumption of 16x16 multiplier by 31%, with 25% area overhead and less than 4% performance degradation in the worst case. The circuit implementation is outlined.

• Type: Conference
• Year: 2002
• Where: APCCAS
• Authors: Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue
• Keywords: APCCAS 2002, Energy-ecient Multiplication Circuits, Hardware, Multiplier Hardware, Power Consumption