NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security

Increasing transmission speeds in high-performance networks pose significant challenges to protecting the systems and networking infrastructure. Reconfigurable devices have already been used with great success to implement lower-levels of appropriate security measures (e.g., deep-packet inspection). We present a reconfigurable processing architecture capable of handling even application-level tasks, and also able to autonomously adapt itself to varying traffic patterns using dynamic partial reconfiguration. As a first use-case, we examine the collection of Malware by emulating an entire honeynet of potentially hundreds of thousands of hosts using a single-chip implementation of the architecture.

• Type: Journal
• Year: 2011
• Where: ARC
• Authors: Sascha Mühlbach, Andreas Koch
• Keywords: ARC 2011, Chip Implementation, Hardware, Level Tasks, Networking Infrastructure