New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination

Abstract— In this paper, we propose a novel common subexpresson elimination (CSE) method to be used for VLSI design of multiplierless finite impulse response (FIR) filter with a small number of adders and registers. The proposed method is an efficient way to reduce the function blocks using the horizontal and vertical CSE. The FIR filters were synthesized from Verilog HDL code. Area and critical path values were evaluated for 0.35 µm standard CMOS library. Compared with the previous CSE techniques, the presented approach can save

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Yasuhiro Takahashi, Michio Yokoyama
• Keywords: Common Subexpresson Elimination, ISCAS 2005, Vertical Cse, finite Impulse Response