A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning

We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the number of hits from increasing the cache size or hit-rates as a function of cache size. Using the counters, we describe a scheme that enables an accurate estimate of the isolated miss-rates of each process as a function of cache size under the standard LRU replacement policy. This information can be used to schedule jobs or to partition the cache to minimize the overall miss-rate. The data collected by the monitors can also be used by an analytical model of cache and memory behavior to produce a more accurate overall miss-rate for the collection of processes sharing a cache in both time and space. This overall miss-rate can be used to improve scheduling and partitioning schemes.

• Type: Conference
• Year: 2002
• Where: HPCA
• Authors: G. Edward Suh, Srinivas Devadas, Larry Rudolph
• Keywords: Accurate Overall Miss-rate, Cache Size, Computer Architecture, HPCA 2002, Memory Monitoring Scheme