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33

FPGA
1998
ACM

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A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs

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A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs

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In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based eld programmable gate arrays. The algorithm is based on a novel iterative procedure for computing all k-cuts of all nodes in a sequential circuit, in the presence of retiming. The algorithm completely avoids ow computation which is the bottleneck of previous algorithms. Due to the fact that k is very small in practice, the procedure for computing all k-cuts is very fast. Experimental results indicate the overall algorithm is very e cient in practice.

Peichen Pan, Chih-Chang Lin

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Algorithm | FPGA | FPGA 1998 | Look-up Table-based Eld | Technology Mapping Algorithm |

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Added	05 Aug 2010
Updated	05 Aug 2010
Type	Conference
Year	1998
Where	FPGA
Authors	Peichen Pan, Chih-Chang Lin

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