As technical systems keep growing more complex and sophisticated, designing software for the safety-critical coordination between their components becomes increasingly difficult. Verifying and correcting these components already represents a significant part of the development process both with respect to time and cost. Scenario-based synthesis has been put forward as an approach to accelerate the transition from requirements to a correct, verified model. In [8], we have presented a synthesis technique for deriving pattern behavior from a set of timed scenarios with parametrized time constraints. The derived patterns can then be verified using our technique for the compositional formal verification of Mechatronic UML models as introduced in [10]. In this paper, we argue that the practical relevance of a synthesis technique predominantly depends rather on its ability to identify and point to specification errors than the complexity of the scenarios it could, in theory, process, p...