A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applic

We propose a pipelined division architecture for low-power ECC applications, which is based on partialdivision on group basis and lookahead technique exploiting the linearity in finite field arithmetic. The throughput is one division per clock regardless of the degree of the dividend polynomial. The salient feature of this architecture is that it leads very low power-delay product. To verify the relative performance of the proposed division architecture over the conventional one using LFSR, three RS and BCH code applications were fabricated using 0.8

• Type: Conference
• Year: 1997
• Where: ISLPED
• Authors: Hyung-Joon Kwon, Kwyro Lee
• Keywords: Division Architecture, Hardware, ISLPED 1997, Low-power Ecc Applications, Pipelined Division Architecture