Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors

One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design methodology for a logic-in-memory architecture where each of memory modules is connected to its dedicated processing element(PE). An efficient memory allocation to minimize the number of memory modules and PEs under a time constraint is proposed based on regularity.

• Type: Conference
• Year: 2006
• Where: ISVLSI
• Authors: Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi
• Keywords: Efficient Memory Allocation, ISVLSI 2006, Memory Modules, Simple Interconnection Network