Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

20

FPL
2009
Springer

favoriteEmaildiscussreport

98views Hardware» more FPL 2009»

Optimal runtime reconfiguration strategies for systolic arrays

14 years 3 months ago

Optimal runtime reconfiguration strategies for systolic arrays

Download www.ccrc.wustl.edu

Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chambe

Real-time Traffic

FPL 2009 | Hardware |

claim paper

Related Content

» Runtime Adaptable Architectures for Heterogeneous Behavior Embedded Systems

» Fast Ant Colony Optimization on Runtime Reconfigurable Processor Arrays

» Minimization of the reconfiguration latency for the mapping of applications on FPGAbased s...

» Elementary block based 2dimensional dynamic and partial reconfiguration for VirtexII FPGAs

» Automatic generation of runtime parameterizable configurations

» Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications

» Strategies for Improving Data Locality in Embedded Applications

» Towards dynamic reconfigurable loadbalancing for hybrid desktop platforms

» Improving SMT performance an application of genetic algorithms to configure resizable cach...

Post Info
More Details (n/a)

Added	24 Jul 2010
Updated	24 Jul 2010
Type	Conference
Year	2009
Where	FPL
Authors	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain

Comments (0)