Optimized On-Chip-Pipelined Mergesort on the Cell/B.E

Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even more problematic with an increasing number of cores. Especially for streaming computations where the ratio between computational work and memory transfer is low, transforming the program into more memoryefficient code is an important program optimization. In earlier work, we have proposed such a transformation technique: on-chip pipelining. On-chip pipelining reorganizes the computation so that partial results of subtasks are forwarded immediately between the cores over the high-bandwidth internal network, in order to reduce the volume of main memory accesses, and thereby improves the throughput for memory-intensive computations. At the same time, throughput is also constrained by the limited amount of on-chip memory available for buffering forwarded data. By optimizing the mapping of tasks to cores, balancing a...

• Type: Conference
• Year: 2010
• Where: EUROPAR
• Authors: Rikard Hultén, Christoph W. Kessler, Jörg Keller
• Keywords: Computations, Distributed And Parallel Computing, EUROPAR 2010, Main Memory, On-chip Pipelining