Optimized Pipelined Parallel Merge Sort on the Cell BE

Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number of cores is expected to rise further, this bottleneck will become more critical in the coming years. Hence, memory-efficient algorithms are required. As a case study, we investigate parallel sorting on Cell BE as a problem of great importance and as a challenge where the ratio between computation and memory transfer is very low. Our previous work led to a parallel mergesort that reduces memory bandwidth requirements by pipelining between SPEs, but the allocation of SPEs was rather ad-hoc. In our present work, we investigate mappings of merger nodes to SPEs. The mappings are designed to provide optimal trade-offs between load balancing, buffer memory consumption, and communication load on the on-chip bus. We solve this multi-objective optimization problem by deriving an integer linear programming formulation an...

• Type: Conference
• Year: 2008
• Where: EUROPAR
• Authors: Jörg Keller, Christoph W. Kessler
• Keywords: Distributed And Parallel Computing, EUROPAR 2008, Mappings, Memory Bandwidth Requirements, Merger Nodes