Out-of-Order Commit Processors

Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications where branch speculation is normally not a problem and where the cache hierarchy is not capable of delivering the data soon enough. In order to support more in-flight instructions, several resources have to be up-sized, such as the Reorder Buffer (ROB), the general purpose instructions queues, the Load/Store queue and the number of physical registers in the processor. However, scaling-up the number of entries in these resources is impractical because of area, cycle time, and power consumption constraints. In this paper we propose to increase the capacity of future processors by augmenting the number of in-flight instructions. Instead of simply up-sizing resources, we push for new and novel microarchitectural structures that achieve the same performance benefits but with a much lower need for resources. Our m...

• Type: Conference
• Year: 2004
• Where: HPCA
• Authors: Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
• Keywords: Computer Architecture, General Purpose Instructions, HPCA 2004, In-flight Instructions, Magnitude Additional Entries