PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches

As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform access latency seen by a core to different independent banks of a large cache spread over the chip necessitates active mechanisms for improving data locality. The central proposal of this paper is a fully hardwired coarse-grain data migration mechanism that dynamically monitors the access patterns of the cores at the granularity of a page to reduce the book-keeping overhead and decides when and where to migrate an entire page of data to amortize the performance overhead. The page-grain migration mechanism is compared against two variants of previously proposed cache block-grain dynamic migration mechanisms and two OSassisted static locality management mechanisms. Our detailed execution-driven simulation of an eight-core chip-multiprocessor with a shared 16 MB L2 cache employing a bidirectional ring to connec...

• Type: Conference
• Year: 2009
• Where: HPCA
• Authors: Mainak Chaudhuri
• Keywords: Computer Architecture, HPCA 2009, L2 Cache Banks, MB L2 Cache, Total L2 Cache