A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection

Abstract--This paper proposes a parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm and applied to the SLAM (Simultaneous Localization And Mapping) problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a Field-Programmable Gate Array (FPGA) coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320

• Type: Journal
• Year: 2008
• Where: TCSV
• Authors: Vanderlei Bonato, Eduardo Marques, George A. Constantinides
• Keywords: Invariant Feature Transform, Parallel Hardware Architecture, Specific Hardware Optimizations, TCSV 2008