Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic

Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choice, but when using a Field Programmable Gate Array (FPGA), other implementation architectures are possible. This work present a hardware implementation of a broad class of integrate and fire spiking neurons with synapse models using parallel processing and serial arithmetic. This results in very fast and compact implementations of spiking neurons on FPGA.

• Type: Conference
• Year: 2006
• Where: ESANN
• Authors: Benjamin Schrauwen, Jan M. Van Campenhout
• Keywords: ESANN 2006, ESANN 2007, Field Programmable Gate Array, Serial Processing, Spiking Neurons