Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory

Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performance for most applications. The industry has already fallen short of the decades-old performance trend of doubling performance every 18 months. An attractive approach for exploiting multiple cores is to rely on tools, both compilers and runtime optimizers, to automatically extract threads from sequential applications. However, despite decades of research on automatic parallelization, most techniques are only effective in the scientific and data parallel domains where array dominated codes can be precisely analyzed by the compiler. Threadlevel speculation offers the opportunity to expand parallelization to general-purpose programs, but at the cost of expensive hardware support. In this paper, we focus on providing low-overhead software support for exploiting speculative parallelism. We propose STMlite, a light...

• Type: Conference
• Year: 2009
• Where: PLDI
• Authors: Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. Mahlke
• Keywords: Automatic Parallelization, PLDI 2009, Programming Languages, Software Transactional Memory, Transactional Memory Models