PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications

Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications. Key features of PARO are: (1) The design entry in form of a compact and intuitive functional programming language which allows highly parallel implementations. (2) Advanced partitioning techniques are applied in order to balance the trade-offs in cost and performance along with requisite throughputs. This is obtained by distributing computations onto an array of tightly coupled processor elements. (3) We demonstrate the performance of the FPGA synthesized hardware with several selected algorithms from different benchmarks.

• Type: Conference
• Year: 2008
• Where: ARC
• Authors: Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich
• Keywords: ARC 2008, Dataflow Dominant Applications, Hardware, Parallel Embedded Architectures, PARO Design Tool