Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs

Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical network topology to a physical one. In this paper, we present an implementation of partially reconfigurable point-to-point (-P2P) interconnects in FPGA to overcome the mentioned overheads. In the presented implementation, arbitrary topologies are realized by changing the -P2P interconnects. In our experiments, we considered parallel merge sort and Cannon's matrix multiplication to generate network traffic to evaluate our implementation. Furthermore, we have implemented a 2D-mesh packet switched network to serve as a reference to compare our results with. Our experiment shows that the utilization of on-demand -P2P interconnects performs 2

• Type: Conference
• Year: 2007
• Where: ARC
• Authors: Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
• Keywords: -P2P Interconnects, ARC 2007, Hardware, Incur Certain Overheads, Logical Network Topology