Performance benefits of monolithically stacked 3D-FPGA

The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and interconnects, are investigated. A Virtex-II style 2D-FPGA fabric is used as a baseline for quantifying the relative improvements in logic density, delay, and power consumption achieved by such a 3D-FPGA. It is assumed that only the pass-transistor switches and configuration memory cells can be moved to the top layers and that the 3D-FPGA employs the same logic block and programmable interconnect architecture as the baseline 2DFPGA. Assuming a configuration memory cell that is 0.7 the area of an SRAM cell and pass-transistor switches having the same characteristics as nMOS devices in the CMOS layer are used, it is shown that a monolithically stacked 3D

• Type: Conference
• Year: 2006
• Where: FPGA
• Authors: Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wong
• Keywords: CMOS Layer, Configuration Memory Cell, FPGA, FPGA 2006, Logic Block