Power-Driven Design Partitioning

In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficiency needs to be improved. In this paper, we propose a power management scheme for FPGAs centered on a power-driven partitioning technique. Our power-driven partitioner creates clusters within a design such that within individual clusters, power consumption can be improved via voltage scaling. We tested the effectiveness of our approach on a set of LUT-level benchmark netlists. Further we did constrained placement of the clusters into predefined Vdd high and Vdd low regions for a single FPGA. Average savings in power consumption with our approach is 48% whereas penalty in channel width and wire length due to constrained placement is 23% and 26% respectively.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Rajarshi Mukherjee, Seda Ogrenci Memik
• Keywords: Constrained Placement, FPL 2004, Power Consumption, Power Mobile Systems