A Power-Efficient and Scalable Load-Store Queue Design

Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.

• Type: Conference
• Year: 2005
• Where: PATMOS
• Authors: Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
• Keywords: Efficient Load-store Queue, Load-store Queue, Modern Superscalar Processors, PATMOS 2005