A Power-Efficient Floating-Point Co-processor Design

According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor cores. This paper develops a SPARC compatible floating-point co-processor, which is part of a SPARC compatible embedded processor, which implements the SPARC V8 floatingpoint instruction set except for square root and all quad precision instructions. To lower the power dissipation of floating-point coprocessor, we modify the decoder stage of the integer unit pipeline to generate the clock gating signals so that the unused floatingpoint co-processor execution pipeline can be clock-gated. The design is implemented in a SMIC 0.18-

• Type: Conference
• Year: 2008
• Where: CSSE
• Authors: Xunying Zhang, Xubang Shen
• Keywords: Compatible Embedded Processor, Compatible Floating-point Co-processor, CSSE 2008, Embedded Processor, Software Engineering