Power minimization using control generated clocks

In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock drivers of sequential circuits. Power savings are achieved by making simple changes to the state machines controlling the datapath. These changes enable the control signals from the state machines themselves to be used as clocksfor the datapath registers. Use of these control generated clocks makes the static timing analysis of des{gns implementing this scheme simpler when compared to techniques such as clock gating. This scheme preserves the cycle boundaries on which registers load data, thereby allowing reuse of fivnctional test cases developedfor the original circuit. In this paper we also describe timing requirements of a design in which this scheme has been implemented, cost-benefit aspects of this scheme and an algorithm for the automatic synthesis of control generated clocks. Resultsfrom application of t...

• Type: Conference
• Year: 2000
• Where: DAC
• Authors: M. Srikanth Rao, S. K. Nandy
• Keywords: Control Generated Clocks, DAC 2000, Datapath Registers, Design Automation, Power Minimization Scheme