Power optimal dual-Vdd buffered tree considering buffer stations and blockages

This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constraint. To tackle the problem of dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices, we develop a sampling-based subsolutions (i.e. options) propagation method and a balanced search tree based data structure for option pruning. We obtain 17x speedup with little loss of optimality compared to the exact option propagation. When dual Vdd buffers are considered, our algorithm reduces power by 23% at the minimum delay specification compared to single Vdd buffer insertion. Moreover, compared to the delay-optimal tree using single Vdd buffers, our power-optimal buffered tree reduces power by 7% and 18% at the minimum delay specification when single Vdd and dual Vdd buffers are used respectively.

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: King Ho Tam, Lei He
• Keywords: DAC 2005, Design Automation, Dual Vdd Buffers, Minimum Delay Specification, Tree Reduces Power