Prototyping Architectural Support for Program Rollback Using FPGAs

This paper presents a processor and memory-hierarchy prototype based on FPGAs that provides hardware support for program rollback. We use this prototype to demonstrate how compiler- or user-controlled speculative execution can help in debugging production codes. The system is based on a synthesizable VHDL implementation of a 32-bit processor compliant with the SPARC V8 architecture. We conduct experiments on applications with real bugs. The applications run on top of a version of Linux ported to this hardware. Our experiments show that our system is able to successfully execute the buggy code sections speculatively. This allows the thorough characterization of the faulty code through repeated rollback and re-execution. Moreover, the hardware extensions we made to the baseline system increase the hardware resource requirements by less than 4.5%.

• Type: Conference
• Year: 2005
• Where: FCCM
• Authors: Radu Teodorescu, Josep Torrellas
• Keywords: 32-bit Processor Compliant, FCCM 2005, Hardware, Synthesizable Vhdl Implementation, User-controlled Speculative Execution