A pseudo-hierarchical methodology for high performance microprocessor design

- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for design control, algorithmic power grid generation, fully customized clock network insertion, timing driven placement and routing, an integrated timing closure strategy, and incremental checking that includes formal netlist verification, DRC and LVS. The methodology places particular emphasis on continuously improving the integration process and incrementally improving both the design and the interoperability of the tools. The final chip tape-out was 17 calendar days from the final netlist.

• Type: Conference
• Year: 1997
• Where: ISPD
• Authors: A. Bertolet, K. Carpenter, Keith M. Carrig, Albert M. Chu, A. Dean, Frank D. Ferraiolo, S. Kenyon, D. Phan, John G. Petrovick, G. Rodgers, D. Willmott, T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. Andrew Scott, Richard J. Weiss
• Keywords: Formal Netlist Verification, Hardware, Integrated Timing Closure, ISPD 1997, Timing Driven Placement