QUKU: A Two-Level Reconfigurable Architecture

FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfiguration to adapt FPGA operation to changing application requirements has been hampered by slow reconfiguration times, and poor CAD tool support. In this paper, a new architecture, QUKU (pronounced cuckoo), is described which uses a coarse-grained reconfigurable PE array (CGRA) overlaid on an FPGA. The lowspeed reconfigurability of the FPGA is used to optimize the CGRA for different applications, whilst the high-speed CGRA reconfiguration is used within an application for operator re-use. An FIR filter kernel has been implemented on QUKU and is shown to have performance which bridges the gap between softcore CPUs and custom FPGA filter circuits.

• Type: Conference
• Year: 2006
• Where: ISVLSI
• Authors: Sunil Shukla, Neil W. Bergmann, Jürgen Becker
• Keywords: FPGA, FPGA Filter Circuits, ISVLSI 2006, Slow Reconfiguration Times