The RACE network architecture

The RACE R parallel computer system provides a highperformance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE system, a parallel computer for embedded applications. The topology of the network, which is constructed with 6-port switches, can be specified by the customer, and is typically a fat-tree, a Clos network, or a mesh. The network employs a preemptable circuit switched strategy. The network and the processor-network interface work together to provide high performance: 160 megabytes per second transfer rates with about 1 microsecond of latency. Priorities can be used to guarantee tight real-time constraints of a few microseconds through a congested network. A selfregulating circuit adjusts the impedence and output delay of the pin-driver pads.

• Type: Conference
• Year: 1995
• Where: IPPS
• Authors: Bradley C. Kuszmaul
• Keywords: Circuit Switched Strategy, Clos Network, Distributed And Parallel Computing, IPPS 1995, Parallel Interconnection Network