RAMSES: A Fast Memory Fault Simulator

In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N3) to O(N2), where N is the memory capacity in terms of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for wordoriented memories.

• Type: Conference
• Year: 1999
• Where: DFT
• Authors: Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
• Keywords: DFT 1999, Memory Fault, Memory Fault Simulator, VLSI, Wellknown Memory Fault