Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation

Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, unlike previous approaches based on levelized-codescheduling,it is not limited to zero- or unit-delaygate models and can provide timing accuracy comparable to that obtained from event-driven methods. We review the synchronous waveform algebra that forms the basis of the Ravel-XL simulation algorithm, present an architecture for its hardware realization, and describe an implementation of this architecture as a single VLSI chip. The chip has about 900000 transistorson a die that is approximately

• Type: Conference
• Year: 1993
• Where: ICCD
• Authors: Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown
• Keywords: Digital Logic Simulation, Hardware, ICCD 1993, Single Vlsi Chip, Synchronous Waveform Algebra