RCDC: a relaxed consistency deterministic computer

Providing deterministic execution significantly simplifies the debugging, testing, replication, and deployment of multithreaded programs. Recent work has developed deterministic multiprocessor architectures as well as compiler and runtime systems that enforce determinism in current hardware. Such work has incidentally imposed strong memory-ordering properties. Historically, memory ordering has been relaxed in favor of higher performance in shared memory multiprocessors and, interestingly, determinism exacerbates the cost of strong memory ordering. Consequently, we argue that relaxed memory ordering is vital to achieving faster deterministic execution. This paper introduces RCDC, a deterministic multiprocessor architecture that takes advantage of relaxed memory orderings to provide high-performance deterministic execution with low hardware complexity. RCDC has two key innovations: a hybrid HW/SW approach to enforcing determinism; and a new deterministic execution strategy that levera...

• Type: Journal
• Year: 2011
• Where: ASPLOS
• Authors: Joseph Devietti, Jacob Nelson, Tom Bergan, Luis Ceze, Dan Grossman
• Keywords: ASPLOS 2011, Hardware Mechanisms, Memory Multiprocessors, Multiprocessor Architectures, Programming Languages