Recognizing Speed Limit Sign Numbers by Evolvable Hardware

An automatic traffic sign detection system would be important in a driver assistance system. In this paper, an approach for detecting numbers on speed limit signs is proposed. Such a system would have to provide a high recognition performance in real-time. Thus, in this paper we propose to apply evolvable hardware for the classification of the numbers extracted from images. The system is based on incremental evolution of digital logic gates. Experiments show that this is a very efficient approach.

• Type: Conference
• Year: 2004
• Where: PPSN
• Authors: Jim Torresen, Jorgen W. Bakke, Lukás Sekanina
• Keywords: Distributed And Parallel Computing, Driver Assistance System, PPSN 2004, Speed Limit Signs, Traffic Sign Detection